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Study Of Single Event Effects On SOI FINFET Device And SRAM Cell

Posted on:2015-08-22Degree:MasterType:Thesis
Country:ChinaCandidate:Z Y YangFull Text:PDF
GTID:2308330464468724Subject:Integrated circuit system design
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With the development of IC design and manufacture technology, the downscaling of the device feature size makes the short channel effect and threshold voltage drift effect more obvious, and thus restrict the device function. As a result, traditional planar device is no longer suitable for the manufacturing process of sub-22 nm technology. Due to the advantages of gate strong control capability and higher integrated density, nano-sized FINFET process emerges to be a good solution to these problems. The introduction of full dielectric isolation process in SOI FINFET, not only removes the latch-up effect which has plagued the bulk silicon devices for ages, but also confines sensitive upset volume in a very small range, so it has a bright application foreground in the field of radiation.In this paper, TCAD simulation study on the characteristics of the tri-gate single-fin SOI FINFET and double-fin SOI FINFET devices in single event effect(SEE) is carried out to compare the sensitivity of these two kinds of devices on the same radiation condition. The three-dimensional models of 40 nm tri-gate single-fin and double-fin SOI FINFET devices are established using ISE TCAD software, then the single event effect module is added for simulation. Drain leakage currents variation with time are extracted from three different factors, which are drain bias, LET values and injection positions separately. The worst case that affects the device of energetic particle injection is obtained, and the influence degree of single event effect on the tri-gate SOI single-fin FINFET and double-fin FINFET devices is compared according to the parameter of pulse current. Simulation results show that the larger the drain bias are applied, the higher leakage collection current peak is. The effect of single particle LET value and distance of single particle injection position with the interface of body region below gate and the fin attributed to drain end is similar. In a small LET value, the double-fin FINFET device drain current is significantly less than that of the single-fin FINFET device; when the LET value increases, the double-fin device drain current is about half of that in the single-fin device, indicating the double-fin FINFET device is less sensitive to SEE than single-fin FINFET device. But when the LET value increases, the gap between that of the two devices decrease.Mixed level simulation of single event effect on SOI SRAM cell is performed using ISE TCAD software, and the obtained sensitive node currents and voltages are compared with circuit level simulation results. In comparison with the reported data, simulation results show that the precision of mixed level simulation method is higher. Considering the coexist of single particle and total dose radiation in space radiation, mixed level simulation of single particle and the total dose coupling on SOI SRAM cell is implemented. The SRAM circuit upset threshold reduces about 0.1 p C/μm compared with the case that only the single particle exists. Namely, SRAM circuit single-event immunity ability is worse under the two kinds of radiation coupling condition.Three typical RHBD circuits including coupled Capacitance added between storage nodes cell, DICE cell and Double-10 T cell are shown, and the SEE mixed level simulations of these circuits are achieved in the same radiation conditions. The advantage of RHBD circuits over traditional SRAM in anti-radiation ability is given by comparing the parameter of flipping threshold. It turns out that the anti-single-event ability of RHBD circuits mentioned above is better than that of the traditional SRAM.
Keywords/Search Tags:SOI, FINFET, SRAM, Single Event Upset(SEU), Radiation Hardened By Design
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