Hardware Design Of Transform And Quantization And Entropy Coding In AVS-S Video Encoder

AVS, the video codec standard of China’s independent intellectual property, is made by AVS working group. AVS-S is developed on the basis of AVS, which is the digital codec standard mainly for the security and surveillance. It can meet the special requirement of the remote surveillance. The putting forward of this standard promotes the development of the security and solves the problem of the barriers in the patent, which helps to reduce a large number of the patent fee.This article does the thorough research of the AVS-S standard firstly, and then analyzed and optimized the algorithms adopted by transform, quantization and entropy coding. Finally, this article does the design and optimization of transform, quantization and entropy coding. According to the characteristics of ICT, the two dimensional ICT transform is achieved by one dimensional transform and transposed matrix of 8x8. One dimensional transform module is reused to achieve the two dimensional ICT transform, which saves the resources of the hardware of the module of transform. The traditional butterfly algorithm is optimized, which makes that the transform coefficients are not needed to reorder and reduces the number of adders. In the process of quantization, this article modifies the method of solving the weighting quantitative matrix, which helps to avoid storing the redundant intermediate variables and saves the resource. The coefficients after quantization are directly deposited to the scan module of Zigzag in the scanning order, which reduces the access of the cache and reduces the time of the encoding. In the process of quantization, weighting quantitative techniques and the traditional quantization can be achieved, which reuse the same module of zoom and quantization, reducing the resource of the hardware. In the process of entropy coding, according to run, level and trans_coefficient, the tables of the codes are compressed, which reduces the complexity of looking up the tables and saves the resources. By redistricting the normal entropy coding and the escaping entropy coding, the complexity is reduced. In this paper, reasonable structure is achieved with the method of pipeline.In this paper, the module of transform and quantization and entropy encoding in AVS-S encoder is achieved by the language of Verilog HDL. The simulation in the function is done on the VCS of Synopsys. The module of reference is established by adopting the reference software of AVS-S standard. By comparing the results of the reference software and the simulation of VCS, we verify the design. Synthesis is done on the Design Compiler of Synopsys. The results show that the design can meet the requirement of the time. Finally, the formal verification is done on Formality.