Design And Implementation Of Image Acquisition Module Based On PLC Monitoring System

Utilizing power line as the communication medium to transmit data and voice signals, power line communication possesses advantage of easy and low-cost network integration and shows a consequent considerable application potential. As a result of the increase of transmission rate and capacity, PLC is becoming the mainstream of network access. Further, the emergence of high-speed power line communication technology makes the transmission of image and video signals through power line possible. Based on orthogonal frequency division multiplexing (OFDM) technique, PLC video surveillance system transmits the video monitoring signal over TCP/IP protocol. The video&voice data transmitted through power line are equivalent to those on local area network (LAN). However, the PLC surveillance network is more convenient and widespread than traditional LAN, which promotes the developments of PLC video surveillance as the mainstream product in Security field.The image acquisition system presented in this thesis, which involves the video A/D conversion module, the video acquisition and data processing module, the control module, the data storage module, and the serial communication module, is the front part of PLC Video Surveillance System and can implement the analog to digital conversion of analog video signal in PAL mode. In addtion, it can provide the accurate storage of a large amount of real-time video data in high speed. The design of the acquisition system includes two parts: hardware design and logic design. Based on the Altera Cyclone series chip EP1C12Q240C8, the main system hardware platform is built, which uses the Cyclone chip, the video A/D chip SAA7113H and the SDRAM chips to constitute the hardware architecture. In the FPGA logic design, the format of data storage is reasonably adjusted in accordance with ITU-R BT.656 standard; and the schedule of read/write SDRAM has been optimized. All the measures mentioned above improves the SDRAM access speed. The schemes of SDRAM operation are suitable for the scenario of large quantity of data storage in short time. On the basis of analysis of data processing and control flow, the thesis partitions the logic functions of video acquisition system as follows: the initialization of A/D module through I2C bus, the decoding of ITU-R BT.656, the control of SDRAM, the operation of serial communication module. The digital logic designs of this thesis are all implemented through FPGA, which increases the reliability, compatibility and versatility.The system is developed under QuartusⅡ7.2 and ModelSim b6.1 software. The printed circuit boards concerned in this system are plotted through Protel DXP. The results of system experiment show that the video acquisition system performs well as designed.