Design And Implementation Of The PON System Based On NetFPGA10G

With the rapid development of information technology, the demand for the qualityof service and bandwidth of network became higher and higher. However, in the lastdecades, though the bandwidth of core network is growing rapidly, the development ofaccess network which is between the core network and customers is relativelybackward. As a solution of optical access network, Ethernet Passive Optical Network(EPON) takes advantage of the valuable resources of the existing Ethernet efficiently,and has been considered as the major solution of optical access network for itscost-effectiveness, high bandwidth as well as easy maintenance.The NetFPGA was designed by Stanford University, it is a low-cost and opensource reconfigurable hardware platform optimized for high-speed networking. TheNetFPGA is built on a high-speed processing hardware and has a programmable andflexible reusable software. In this paper, we detailed the existing EPON simulationplatform and the in-deep study of the key technology of PON as well as thedevelopment and application of NetFPGA10G. Then, we designed a NetFPGA10G-based PON system. The main work is divided into the following sections:(1) This paper describes the background, significance and research status at homeand abroad of EPON and NetFPGA10G platform. The hierarchical model, workingprinciple and existing simulation platform of EPON is also investigated. Besides, wediscussed the necessity of the realization of NetFPGA10G-based PON system.(2) The function of pipeline module and the data processing flow are introducedand the AXI4-Stream protocol is also studied in order to implement the communicationlink among modules.(3) Considering the functional differences between Optical Line Terminal (OLT)and Optical Network Unit (ONU), we designed the OLT and ONU separately asfollowing.Choose reference NIC project as our reference project, which has the simpleststructure and working at the same layer as PON in the OSI.Follow the modular rule strictly, which is benefit for reducing the complexity ofmodules. Adopt three-state machine during programming due to Mealy state machine iseasily affected by input signals.Adopt a back buffer mechanism in order to facilitate the management ofbroadcasting packets and GATE messages.The NetFPGA10G-based PON system is implemented using Verilog HardwareDescription Language (HDL). Then, we put the OLT/ONU core module into NetFPGA10G pipeline by ISE, XPS and other Xilinx tools. The project has completed thefunction of downstream and upstream transmission of PON, MPCP protocol as well asother Ethernet function. Furthermore, a simulation has also been conducted at last.