Hardware/Software Co-design Method For Lossless Audio Decoding Based On RISC Core

Lossless audio compression formats have the feature of completely restore the original audio data to ensure sound quality. APE can get higher compression ratio than other lossless compression formats. Due to apply a completely symmetrical algorithm, APE decoding algorithm has the same complexity with the encoding algorithm. Especially at high compression levels, APE decoding algorithm has a high performance requirement for embedded processor. By analyzing the application characteristics of APE decoding algorithm, this paper focus on an software and hardware co-optimization method for lossless audio decoding based on the embedded processor RISC32.This paper first discusses the APE codec algorithm processes, which consist of mid/side encoding, predictive encoding and entropy encoding. We focus on two key technologies:predictive encoding and entropy encoding in lossless compression algorithm, and further describe their implementations in APE encoding algorithm. The predictive encoding technique used by APE encoding algorithm is linear adaptive neural network predictive encoding algorithm, and the entropy encoding technology used here is an combination of range encoding and RICE encoding.By analying the application characteristics of APE decoding algorithm, we optimize entropy decoding algorithm and neural network predictive decoding algorithm. For entropy decoding algorithm, the key function range_get_symbol₃980is optimized, including simplifying lookup table and reducing the load operation of high frequency events. For neural network predictive decoding algorithm, according to the characteristics of the continuous multiplication instructions executed by RISC32microprocessor, we do assembly language optimization of function scalarproduct to speed up multiplication operation. The experimental results show that, compared with baseline algorithm, under different compression levels, the speedup of the performance of APE decoding algorithm is8.31%on average and the average power consumption increased by5.2%, respectively.By analying the operation characteristics of APE decoding algorithm, we optimize multiply_accumulative and division modules in RISC32microprocessor. For APE decoding algorithm,75%of multiplication operations are16-bit, we optimize the multiply_accumulative module, makeing it enable to implement two kinds of multiplication operations, including32×32bit and32×16/16×16bit patterns. The performance of multiplication increases42.80%. Based on the data characteristics of divisor, we optimize the division module, making it enable to save unnecessary cycles by shifting. The performance of division increases26.50%. We also compare two kinds of cache writing strategies, results show that compared with write-through method, the performance of processor decoding APE algorithm under write-back method only increases0.32%, but it can reduce the utilization rate of bus by61.81%. The experimental results show that, under different compression levels, the speedup of the performance of RISC32processor decoding APE algorithm is9.88%. The increasing area is about40,940gates and the average power consumption reduced by5.20%.