FPGA Implementation Of On-chip Multi-core Distributed Processing Mechanism

Distributed processing is a hot research topic at present, yet its implementation and optimization are based on software platform. In this study, the design scheme of on-chip multi-core distributed processing mechanism based on hardware (FPGA) is proposed.Heterogeneous multi-core chips are widely used in top layer supercomputers nowadays; and similar heterogeneous processing units (or computing accelerator) are ubiquitous in FPGA systems. In multi-core chips and FPGA systems, on-chip network plays a key role for the connection of these processing units. However, the current on-chip network is applied only to the point-to-point communication between on-chip component and the memory interface. With the continuous increasing of system nodes, traditional programming methods such as MPI cannot make best of on-chip and off-chip network, making communication the bottleneck of performance.A messaging passing engine is put forward in this study, which achieves hardware point-to-point and collective communication as part of the on-chip network. On the one hand, messaging passing engine significantly improves communication performance by taking up the workload of general-purpose processing unit. On the other hand, message passing engine directly provides interfaces to heterogeneous processing units, which reduces or even removes the surrounding data channels of the operating system and library. Experimental results show that message passing engine can greatly reduce the communication time and improve the overall performance, especially for heterogeneous computing systems and tightly-coupled networks. In addition, the results indicate that message passing engine can undertake communication tasks efficiently so that the processing units can be fully devoted to computation.The hardware platform in this design is Xilinx Virtex-5FPGA development board, the MicroBlaze processor embedded in it can work as a central processor. Because of the32-bit RISC (Reduced Instruction Set Computer) optimized architecture, MicroBlaze core occupies few on-chip resources, simple and of high performance. On the basis of an in-depth study of existing distributed processing software implementations, the basic functions of point-to-point communication and collective communication in distributed processing are executed with VHDL in Xilinx ISE10.1. Simulation and validation are performed on each function and the overall design. A hardware project is created with Xilinx EDK and the hardware distributed processing mechanism is added to the hardware project to generate related files including bit stream and netlist for board verification.