Research On Bit-width Optimization With Affine Arithmetic

With a series of advantages, such as customizable, parallelism, configurable,low-power dissipation etc, FPGA has become one of the ideal embedded computingplatform, and has been widely used in the areas of aerospace, high-performancecomputing and information processing. For FPGA based calculations, floating-pointarithmetics are usually transformed to fixed-point arithmetics, which can obtainfaster speed and lower power consumption. In the process of transformation, one ofthe main problem is to select the appropriate bit-widths, as bit-widths of signalshave a great impact on the performance of resource consumption, speed, accuracyand power dissipation. In this thesis, we conduct research on this problem.Firstly, research on the affine arithmetic, which is widly used in the process ofbit-width optimization. The approximate methods of affine arithmetic ignore thecorrelations between high-order noises, which leads to inaccurate calculation results.Aiming at this problem, an improved high-order noise correlation affine arithmeticapproach is proposed. By changing the calculation method of the second-ordernoise in multiplication, the approach can ensure non-negative product of even-ordernoises. Therefore, it achieves better tradeoff between computational accuracy andcomplexity.Secondly, some research on the implementation of bi-twidth optimizationbased on IHNCAA have been conducted. First of all, the IHNCAA is applied to theprocess of range analysis, according to its principle. Then, aiming at the deficiencyof existing bit-width optimization process and error calculation model, a modifiedcalculation model of error is proposed, making the range analysis and presicionanalysis can been done at the same time. In the end, the proposed bit-widthoptimization methods are implemented in the Linux operating system. Besides, therules of IHNCAA are overloaded as operators to increase the universality of thesoftware program.Finally, we analyse and test the performance of the bit-width optimizationmethod based on IHNCAA, and appliy it to the FPGA designs of FIR digital filterand sine function. Experiments show that, the proposed method named IHNCAA is a better combination of chebyshev approximation and trivial range estimation. Itperformes better compromise between speed and accuracy. After the optimizationby the proposed method, the instances’ performance of hardware implementation issuperior to other existing bit-width optimization method and the bit-width designrules of DSP Builder. All of the results further illustrate the effectiveness of theproposed method.Besides, our research is not only beneficial to reduce the implementation costsand improve the performance of the FPGA based designs, but also has significantreference to the ASIC design aiming at computing.