FPGA Prototype System Design Of OFDM Power Line Communication

Power line communication (PLC) uses existing power lines to transmit signals without needingnew communication lines. It has a series of advantages, such as low cost, short period, easy to installand use. And it is wildly used in areas of smart grid, intelligent household, intelligent transportationand other areas. Recently, PLC based on orthogonal frequency division multiplexing (OFDM)technology is adopted by several international PLC standard organizations and becomes a researchhotspot in PLC field. The G3-PLC standard based on OFDM is a narrow band PLC standard, which isinitiated by the French electricity sales company ERDF and designed by Sagemcom and Maxim forthe smart grid. Based on the research of relevant G3-PLC algorithms, a FPGA prototype system ofOFDM-based PLC is designed. The main works are shown as follows:1. On the basis of G3-PLC timing synchronization algorithms, the improved timingsynchronization algorithm based on local sequence correlation is proposed, and the simulation of theimproved algorithm is done. The analysis result indicates that the improved timing synchronizationalgorithm has higher accuracy and wider work scope of SNR.2. Aiming at the particular G3-PLC pilot structure, a channel estimation method based on cycletraining sequences is proposed. It has low complexity, low resource consumption and it is compatiblewith a variety of transmission modes. The simulation result shows that the proposed method has betterchannel estimation performance, especially under the condition of low SNR.3. Based on the G3-PLC, a fixed-point simulation platform of the physical layer transceivermodule in MATLAB is set up, which provides the basis for the FPGA prototype system design. Thestructure of the FPGA prototype system is optimized by fixed-point simulation. And a total designscheme of G3-PLC physical layer prototype system is proposed. It is compatible with a variety oftransmission modes, fully considering the system performance and resource consumption.4. FPGA code design of G3-PLC physical level transmitter module is completed, includingscrambler, RS encoder, convolutional encoder, repetition encoder, interleave, mapping and OFDMmodulation. The output signals of FPGA transmitter are compared with the fixed-point simulation signalsto verify the design result.5. FPGA code design of G3-PLC physical level receiver module is completed, mainly includingframe synchronization subsystem, automatic gain control subsystem, OFDM demodulator, channeldecoding subsystem and so on. Based on the signal processing hardware platform in laboratory, experiment has been carried out. And the results verify the correctness of the designed prototypesystem. In this experiment, XC6SLX150T of XILINX FPGA is used and the resource consumption ofthe receiver module is about15%of the total resources.Design and verification of G3-PLC physical layer prototype system is completed in this paper. Itlays a solid foundation of the further IC design and has important significance for wide application ofOFDM PLC technology in our country.