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Research And Design Of A High-efficiency BOOST DC-DC Converter With Peak Current-mode

Posted on:2017-01-30Degree:MasterType:Thesis
Country:ChinaCandidate:L XuFull Text:PDF
GTID:2272330509959640Subject:Electronic Science and Technology
Abstract/Summary:PDF Full Text Request
With the rapid development of portable electronic devices, switching regulators have been widely used around the world for the features of small size, high efficiency and high power density. It has become a hot research topic for recent years.This thesis firstly addresses the topologies, the principles, the modulation modes and the feedback mechanism of DC-DC converters. Then, a high-efficiency Boost DC-DC converter with the peak current control mode is designed, which has the advantages of fast transient response, simple compensation network and embedded current limit. Meanwhile, a high transfer efficiency is achieved with the method that the operation mode can automatically switch from the PWM mode to PSM mode under the light load condition. Besides, several kind of protection circuits are also integrated in the chip, such as under-voltage lockout circuit, thermal shutdown circuit, etc. The whole chip structure is designed according to the specifications of the DC-DC converter system, and the efficiency of the system is analyzed according to the sources of power loss. The relevant solution on stability is proposed based on stability analysis of the actual circuit system. Each sub-block of the DC-DC converter system is designed and simulated. The main innovations are as follows: Firstly, a novel error amplifier with integration of multi-functions of peak current-mode DC-DC converters is presented which realizes the functions of soft-start, operation mode switching(from PWM mode to PSM mode) and maximum peak current limit. The circuit is simple and easy to implement. Secondly, an on-chip ramp voltage generation circuit is integrated by applying pulse-skipping and narrow pulse charging technology. The slowly rising ramp voltage with using a small capacitance is obtained by combining the ramp voltage generation with multi-functions error amplifier circuit, and a smooth transition from the start-up state to a steady state is also achieved. The inrush current is effectively eliminated during startup process by the soft-start functions, and the output voltage rises smoothly without overshoot.Under Cadence Spectre design environment, the simulation of the circuit and system are completed based on CSMC 0.5μm 25 V BCD process. The input voltage range is from 3V to 7V, and the output voltage range is from INV to 12 V with fixed 1MHz of switching frequency. With the typical application condition of VIN=5V、VOUT=12V、L=10μH、COUT=10μF and the load current from 0 to 500 mA, the simulation results show that the maximum output voltage ripple is less than 30 mV, and the efficiency is above 90% when the load current changes from 5mA to 500 mA. The DC-DC converter possesses the features of low ripple coefficient, low power consumption, good line regulation, fast load transient response and high efficiency, etc.
Keywords/Search Tags:DC-DC converter, The peak current mode, Under-Voltage lockout, An error amplifier, The soft-start
PDF Full Text Request
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