A Ka Band PLL Design For Near Space Vehicle

This thesis described the research background of near space, given phase-locked loop applications on near space vehicle, and introduced the history and knowledge of the phase locked loop. In this paper, the basic principle, performance optimization and circuit implement of the Ka band PLL were studied.Firstly, a systemic analyze for the work mechanism of PLL was presented. Each module’s performance and the influence on PLL were analyzed, some ways to optimize the phase noise was provided too. The detailed flow to design a PLL system which had best phase margin was given. Secondly, according to the systemic analyze, the specific circuits design was implemented. The PFD was constituted by DFF with a reset terminal. In order to generate two opposite-branch signals, inverter chains were added to the DFF’s outputs. To strength the symmetry of signal, latch was used on inverter chains. A novel charge pump based on the operational amplifier was proposed. The proposed charge pump had perfect current matching characteristic. A reconfigurable VCO was designed to meet the requirement of two:output frequency, and the noise filtering technology was employed to optimize the phase noise. The divider was designed based on E-TSPC structure. E-TSPC structure can reduce power consumption and the area of layout. Finally, the physical layout of PLL was completed. In the design of PLL’s layout, the symmetrical layout was used on VCO, Divider, PFD and LPF to reduce power consumption. Due to the high operating frequency of VCO, a guard ring was added to reduce extra noise.This thesis was design in SMIC 180nm Mixed-Signal 1P6M CMOS technology. The simulation and layout design were also completed. The area of the layout was about 73mm. The maximum power consumption was 45.12mW in each frequency band, the output phase noise was less than -90.1dBc/Hz@1kHz,-101.01dBc/Hz@10kHz,-115.7dBc/Hz@100kHz, and the lock time of the PLL is less than 5us. The PLL meet the design specifications.