The Design Of Core Module In The AVS Video Decoder

AVS (Audio Video coding Standard) video standard is the audio and videocompression standard based on independent-innovation technique of China andinternational open technique. The high-definition video decoder based on AVSstandard is characterized of high compression rate and low calculation complexity.The AVS decoder is available for digital TV, phone video conference, PSP videoplayer, and MP4. The video decoder chip based on independent-innovation techniquemakes the local digital product break away from the dependency to oversea companyand improves independent R&D consciousness.This paper mainly introduces the ASIC front design of intra prediction and interprediction in AVS decoder through understanding the picture pattern, compress style,video stream syntax and semantic based on AVS video coding standard and theprocess of decoding. Entire design is simulated and verified with Synopsys VCS andsynthesized and optimized with Synopsys DesignWare IP library and HJTC 0.18umCMOS library. The AVS decoder is available to AVS JiZhun profile and 4.0 level.The specification of the prediction module in the AVS decoder is 1.8V workingvoltage, almost 100MHz frequency. The power consumption of prediction moduleshould under 150mW and the area of logic cell should lower than 100,000 gates.Finally, after the synthesis and optimization in Synopsys Design Compiler, thesystem dock frequency is 100MHz and there is divided dock in the sub-module.After the optimization by Synopsys Power Compiler, the total power consumption ofprediction module is 127.82mW and the total logic cell area is 1872834 um~2. Theresult meet the requirement of AVS decoder.