Study On Trough-Silicon Via Etch And Related Processes For Memory 3D Stack

Driven by the need for improved performance and the reduction of timing delays, methods to use short vertical interconnects have been developed to replace the long interconnects found in 2D structures. The market for 3D integration includes many applications ranging from imaging products and memory to high-speed logic and processing applications. Some 3D integration is planned for military-related products. The industry is moving past the feasibility (R&D) phase for TSV technology into the commercialization phase. 3D TSV will become a reality for flash or image sensors by early 2008.Our research delivers an integration scheme including wafer bonding in advance, and then thinning, TSV (through-silicon via) for NAND Flash and DRAM memory stack. This paper mainly targets on the TSV etch.TSV can be carried out by laser drill and DRIE (Deep Reactive Ion Etch). Considering the thermal impact and particles contamination, laser drill is not our choice. Without those concerns, DRIE also provides a high-speed and very good anisotropic etching for silicon, and gets very high selectivity etching over photo-resists. Through continuous experiments and optimizations, we achieve a 30um width 70um depth TSV etch process, which is featured by improved uniformity, minimized sidewall scalloping and undercut. The via-diameter-scaling is our next goal.