Study On Deep-submicron Placement And Routing Method Based On Encounter

Half a century has passed since the invention of integrated circuits. With the rapiddevelopment of integrated circuits, the chip integration is more and more high, the scalegets more and more big and the feature size becomes more and more small. Theintegrated circuit has penetrated into every aspect of modern life. Moderncommunicating, medical and transportation system all depend on the integrated circuits.However, development has also put forward higher challenges on design method, suchas cross talk effect caused by feature size shrink, and the timing becoming complicatedbecause of the interdependence of many design variables. Therefore, we need todevelop a mature back-end design process so as to effectively eliminate these problems.This paper studies the back-end physical design process of an ASIC based on atool named Soc Encounter of Cadence. The layout is displayed and taped out in SMIC0.18μm CMOS process. It also analyses the process and theory of P&R and hascompleted routed the module of AGC.The backend design is divided into data preparation, floorplan, cell placement,clock tree synthesis, static timing analysis, routing and so on. This article focuses onclock tree synthesis and static timing analysis. Through the comparative study on thethree groups of experiments, a method driven by specially big clock buffer and clockinverter is proposed to assess the clock tree synthesis, which can improve the quality oftiming. Do the STA after CTS and after routing respectively, and finally it fixes all theviolations and meets the timing. At the same time, the paper studies related content ofDFM, with emphasis on antenna effect and its correct methods.