The Device Characteristics Research Of AIN/GaN Heterostructure Field-Effect Transistors

In recent years, with the development of materials growth technique, as the representative of Ⅲ-nitride heterostructure materials, AIN/GaN has received more and more attention from scientists all over the world. Compared to the traditional AlGaN/GaN heterostructure material system, AIN/GaN has much larger conduction band offset(1.897eV), larger spontaneous and piezoelectric polarization effect, thus it can gain larger two-dimensional electron gas (2DEG) concentration and better carrier confinement. Even without any anthropic doping, AIN/GaN electron devices can possess a high mobility2DEG density of the order-1013cm2at the AIN/GaN interface quantum well. Because of its high2DEG density, high electron saturated velocity, high breakdown voltage etc. AIN/GaN heterostructure field-effect transistors (HFETs) enjoy broad prospects in high temperature, high frequency, high power electronics application field.The research of AIN/GaN electronics devices has been carried out for many years, and a set of progress have been achieved, but the existence of several problems limited the AIN/GaN HFETs from a large-scale commercial process. For instance, because of the limit of growth technique, high quality of A1N barrier layer lattice structure and AIN/GaN interface profile are hard to achieve; the measured2DEG density and electron mobility of the AIN/GaN HFETs are much lower than theoretical calculation results; large lattice mismatch between A1N and GaN layer, which leads to high concentration of trapping states generated at the heterostucture interface. Thus, further study of the material and device characteristic parameters is important to the AIN/GaN HFETs development. Taking these existing problems into consideration, the main work in this thesis is to study the effect of strain variation in A1N barrier layer about polarization sheet charge density and electron mobility, and trap states characterization at AIN/GaN interface. The main conclusions of the thesis are list below: 1. The strain variation in AIN barrier layer of AIN/GaN HFETsWe theoretically calculated the polarization sheet charge density confined at AIN/GaN interface through lattice constant model. Then based on the measured C-V and I-V characteristics, the polarization charge density is calculated through self-consistently solving Poisson’s and Schordinger’s equations experimentally. Compared the calculation results between the two methods, we found that the device polarization charge density is much lower than the theoretical result, and further study showed that the traditional spontaneous polarization equation is no longer fit for the new AIN/GaN material system. This can be explained as follows:As large lattice mismatch and thermal mismatch exist between AIN and GaN layer, strain relaxation will be generated during the growth process and further affect the strain distribution in epitaxial layer. Further more, the Ohmic annealing process can also leads Ohmic metal atoms lateral diffusion which will have effect on ultra thin AIN barrier layer. At the end of this chapter, we analyzed the effect of floating gate on AIN layer in AIN/GaN HHETs.2. Interface trap states in (Ni/Au)-AlN/GaN SBDsThere are four main possibilities to consider for spatial location of traps in (Ni/Au)-AlN/GaN SBDs,:(1) the metal-semiconductor interface of the Schottky contact,(2) the bulk of the barrier layer,(3) the interface between the barrier layer and the channel, and (4) the bulk of the channel layer. Different traps will result in a dispersion of capacitance at different regime of C-V characteristics. Based on the measured C-V curves, we demonstrate that the trap states in our samples are mainly located at the AIN/GaN interface. Along with the measured I-V curves, G-V curves and the equivalent models of AIN/GaN HFETs, the density of interface traps, the time constants and the trap states energy were calculated. Compared the results with that in AlGaN/GaN HFETs, we found that the density of interface trap states density in Al/GaN SBDs is about one order of magnitude larger than that in AlGaN/GaN devices. And we attributed the difference to the large lattice and thermal mismatch between AIN barrier layer and the GaN channel layer. In addition, Ohmic contact annealing is another important factor for the generation of high concentration of interface trap states in (Ni/Au)-A1N/GaN SBDs.