Research Method For Extension Of The SRAM Compiler’s Capacity

Nowadays, With the rapid development of the integrated circuit. The design of embedded SoC has been a hot topic. And the embedded memory will dominate in the whole SoC system in the future, and the rate is reaching higher and higher. Static Radom Access Memory (SRAM) is famous for its high speed which is used in high-speed devices such as CPU cache and the device for high-performance communication networks in memories. The study for SRAM technique mainly consists of two directions that are high speed and low power, The SRAM products trend to different directions based on what the customers need.There are two methods for the design of SRAM, One is full-custom design which has a long design cycle usually takes a few months and even several years. Then we adopt the other method called compiler technique which can generate different sizes of SRAMs that the customers need. Compiler technique is a method of semi-custom design which divide the SRAM into small modules, These modules are relatively fixed and they are full-custom designed and to establish the library which form the basic unit library, Then compiler stack the basic units from the library to complete the SRAM circuit by certain rules. It has many advantages by using compiler technique:(1) Designers can concentrate on the systematic design by shortening the design cycles heavily;(2) It saves the design resource and improve the reusability of the design resource;(3) It improve the design efficiency by changing the level of the design transition. So compiler technique is the mainstream one in the design of SRAM.The research in this paper is based on a SRAM Compiler which is completed previously, Its parameters have a depth of16-8192words and a width of2-32bits, which is configurable, The maximum capacity of SRAM that the former compiler can generate is256Kb. This paper is aim to make an extension of the former compiler’s capacity to realize extensional parameters that have a depth of1K-512K words and a width of8-32bits, which is configurable. And it means that The maximum capacity of SRAM that the new compiler can generate is2MB. The extension of compiler’s capacity for main idea is to use the SRAM of small-capacity which the former compiler can generate as the basic stitching unit and use block method and tiling method to complete SRAMs of large-capacity by certain stitching structures.