| Because parallel comparison can obtain high-speed, Content Addressable Memory (CAM) is widely used in many applications which require fast table lookup. Such as the fully associative TLBs (Translation Look-aside Buffer) in Micro-processors, Tag comparator in Cache design, image encoding, Huffman coding and decoding and so on. However, the large power consumption of CAM would be vital for these advanced applications. In addition to how to improve the matching speed of CAM, how to decrease the power consumption and enhance the operating stability has become a research focus. The purpose of this thesis is to achieve a CAM design with lower power and higher stability, and the focus is the optimized design of the hybrid-type CAM architecture.Firstly, this paper makes a summary of the design methods of the low power CAM at home and abroad, and explains the whole framework of the CAM in detail. Then the thesis puts an emphasis on the analysis of the mach line (ML) structure of CAM, especially on the hybrid type matching line structure. Furthermore, a comparative study has been made among the existing hybrid type CAM designs. Finally, an optimized hybrid-type match line structure of CAM is proposed, and this structure can cut down the average power consumption largely by decreasing the voltage swing of match line about a threshold voltage, while improving the operating stability by means of changing the discharge path of match line which reduces the level jitter on match line. Moreover, the layout of this proposed structure has been plotted, and the corresponding post-layout simulation result is expatiated.On the basis of the SMIC65nm Standard CMOS process, the supply voltage is1.2V, simulation dates show that the voltage swing of ML has been decreased about350mV, which makes the average power consumption been reduced by23%comparing to the existing hybrid-type structure. In addition, the level jitter on ML is also improved by660mV (from1.09V to0.43V), which reduces the matching error rate. |
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