Condition Code Optimization In Binary Translation System For ARM

Binary translation system is a bridge between codes of different platforms, while the performance of the system restricts its application. It is an important issue how to improve the performance of binary translation system. In such systems, after data flow analysis on those flags the translation of conditional flags still needs plenty of native instructions which greatly affects the performance of systems. Because MIPS does not have a register which called Program Status Word, while ARM has such a register, then to simulate the function of the ARM instruction inevitably requires a lot of MIPS instructions to achieve. In the binary translation system, how to choose the right and proper way MIPS instruction, efficient completion of the ARM instruction function is the key to solving the problem. Existing optimization flag is the flag bits as much as possible to avoid redundancy analysis processing flag value, thereby reducing the MIPS instruction generated translation, but for non-redundant bit flag value, an instruction still requires a large translation. This has led to a great expansion of the code generated translation, directly affects the performance of the binary translation system.To solve this problem, a flag pattern optimization method is presented, this method which is based on data flow analysis makes flag definition and flag usage ARM instruction a fixed pattern, and depending on different patterns to achieve the same semantic by choosing appropriate MIPS instructions. This method can effectively reduce the amount of MIPS code generated by translating, and can improve system performance. Experimental results show that MIPS code generated by translating has a14%reduction, and the system performance is improved by13.7%.