Design And Implementation Of LBT In JPEG XR Image Compression Based On FPGA

As the development of technology and the increment of people’s requirement, the digital cameras can catch higher dynamic range and more delicate images. However, the challenge to storing equipment and image communication is very huge. A valid and common method to solve this problem is image compression. In2007, the Joint Photographic Experts Group released the newest static image compression standard-JPEG XR. Its core transform is Lapped Biorthogonal Transform (LBT). LBT is a kind of frequency domain transform based on Discrete Cosine Transform. Because the LBT is also applied to boundary pixels, the "blocking effect" will be reduced efficiently. Meanwhile, owing to the feature of Field Programmable Gate Array (FPGA), the applications of image signals processing based on FPGA extended increasingly in the recent decades.This paper designs a LBT’s implementation in JPEG XR image compression based on FPGA. The system uses the Genesys FPGA development board and the VmodCAM image acquisition board as the hardware platform to get the image and finish its LBT computation. And then the results will be sent to the PC through UART port to assist in system debugging.There are two parts in the whole system:image collecting part and LBT computing part. The image collecting part mainly includes three modules:image collecting, image cache and image display. Firstly, the system gets the image by the VmodCAM board. And then the image will be stored in the image cache. The image display module will display the image on the monitor through VGA port. The LBT computing part mainly includes two submodules: Photo Overlap Transform (POT) and Photo Core Transform (PCT). POT and PCT consist of some basic function modules, such as Hadamard transform, scaling, rotation, etc. Because of the limit of resource, the input of LBT computing is portion of the collected image (32X32pixels). The results will be sent to PC through the UART port. All modules of the system are designed in Verilog HDL. To verify the correction of the LBT computing part, we will compare the results got by FPGA with the results got by C program. If they are the same, the LBT’s design and implementation based on FPGA is right. After debugged and improved repeatedly, the system can achieve the expected results.