Software And Hardware Co-design For The Optimization Of Mp3Decoder Based On FPGA

At present, portable MP3players are very popular. The current productsemployed the ASIC or DSP unit as the decoder of MP3files. The ASIC one is able toachieve limited functions and does not support update. The DSP one is amulti-function scheme, able to be updated by software. Now, since the FPGA (FieldProgrammable Gate Array) chips are popularized, the parallel computing capability ofFPGA can be utilized to accelerate MP3decoding process.This thesis proposes an optimization design of the MP3decoder based on FPGA.It uses the software and hardware co-design to attain the hardware acceleration on theexisting software decoding algorithm, decreasing the development period. After theanalysis of the MP3decoding process, the design of the MP3decoder can be dividedinto software and hardware partition according to the calculation complexity. Thehardware part is achieved by logical slices on FPGA, whereas the software part isdone by exsting software decoding library.During the MP3decoding process, there are plenty of recursive multiplicationsin Inverse Modified Discrete Cosine Transform (IMDCT) and sub-band synthesisfilter. Both of them can be accelerated by hardware. In the design of sub-band filter,by using butterfly computation and statemachine, it can be accomplished smoothly.However, for IMDCT, because of the amount of branch statements, it is not suitable touse the same structure. Therefore, a co-processor is used to work with the mainprocessor in parallel, accelerating the decoding process.In order to verify the functions of each hardware component, corresponding testprograms are writen. Finally, all of the hardware components and software modulesare integrated to be testified.The experiments show that the execution time of IMDCT and sub-band synthesisfilter has been decreased by30.97%and71.28%, respectively. After the optimization,the performance of MP3decoder fulfills the design requirements.