1.6GHz~3.2GHz0.18μm CMOS Wideband And Low Phase Noise VCO Design

Voltage-Controlled Oscillator（VCO）is a critical device of radio frequencytransceivers. It works as a local oscillator（LO）for frequency translation. The tuning rangand phase noise of VCO are the most desired specifications which dominate the workingfrequency, selectivity and sensitivity of the receivers. However, the character of high flicknoise of submicron CMOS devices make the designing of wideband and low phase noiseVCO based on CMOS process became a huge challenge in modern wirelesscommunication system.In the trend of system-on-chip and compatible with a variety of wirelesscommunication protocols, VCOs with better performance are required. Just based on thisbackground, a1.6GHz~3.2GHz wideband and low phase noise VCO is designed in thisthesis which can apply in wireless communication terminals. Firstly, this papersummarizes the currently research situation and development trend of VCO, then the basicprinciples and some popular phase noise theories are briefly introduced. Lastly, the designsteps and key research points of a wideband LC VCO are elaborated. This paper adoptsthe complementary cross-coupled full differential LC VCO topology to realize function ofoscillation, and then uses6bits of switched-capacitance branches to divide the tuningrang into64sub bands, which can not only low the gain of VCO frequency (Kvco) but alsoextend the tuning rang. At the same time, an automatic amplitude control (AAC) circuit isproposed to stable the amplitude of VCO output. The AAC circuit adopts positive peakdetector to trace the maximum of the VCO output signals and feedback to adjust the gatevoltage of the tail current MOSFET, which makes VCO biased at the optimal valueimproving the phase noise performance. In order to low the PVT (Process, Voltage,Temperature) effect and quicken the PLL lock speed, an automatic frequency control(AFC) is proposed, which uses binary algorithm to search the optimal sub-band. In theend, the layout of LC VCO is designed.This VCO is designed and validated by TSMC0.18μm1P8M RF CMOS process.The simulation results show that the tuning rang is1.52GHz to3.43GHz, the tuning ratioachieves77%and the phase noise is-119dBc/Hz@600kHz at3.2GHz. Furthermore, the results show the AAC circuit stables the tank amplitude at1V decreasing the amplitudechange rate by90%. Finally, the mixed signal modular of PLL with AFC is simulated bySpectre-Verilog emulator, and the PLL coarse calibration time is less than6μs.