Research And Design Of Leon3-based Hardware-software Co-verification Environment

With the rapid development of integrated circuits, it is becoming a mainstreamto design more powerful and complex SoC. However, the increasing size of SoCmakes verification more difficult. To solve the problem, designers proposedhardware and software co-verification, and promoted by companies and collegesaround the world, the hardware and software co-verification technology developsrapidly. However, compared with foreign technology, the domestic technology inthis area is still not mature enough. Therefore, it is of great importance to continueto do research in this area.Based on existing schemes, this paper adopts FPGA-based hardware andsoftware co-verification for the simulation acceleration, which is theoreticallyprovedfeasible. On the PC-end, this project utilizes simulation tools and winsockAPI to construct downstream channel that generates and transmits stimulus. On theFPGA end, this project utilizes the SoC based on Microblaze to construct upstreamchannel that is responsible for simulation data loading and results feedback. Bothends complete physical transmissionthrough Ethernet and reach the accelerationpurpose with the advantage of FPGA high frequency. In the basic scheme, theproject constructs hardware and software co-verification platform. Because of thewide applicability of leon3-based SoC, the project finally builds hardware andsoftware co-verification environment based leon3.This project is implemented on the basis of customized scheme. The platformis mainly divided into the PC end, FPGA end and Ethernet interface. The PCendincludes a simulation module and a data control module, which is primarilyresponsible for generating, controlling and transferring stimulus. The design ofFPGA end mainly includes clock management unit and cooperative control module,which are designed for the completion of the transfer of stimulus along with thePCend load to the test module and the clock will return to work in response. TheEthernet interface section has hardware and drivers two levels, which are used fordata transmission and control between PC-end and FPGA-end. After overall designand implementation, leon3processor is ported to the entire platform and theleon3-based hardware and software co-verification environment is built.After all design work completed,8-bit adderbased on non-pipelined sequentialcircuit, pipelined sequential circuit and combinational logic circuit is used as a testmodule to test the basic function of the platform. The result shows that the platformhas accelerated functional verification. Finally, APBuart is used as a module to be tested to verify leon3based hardware and software co-verification environment.The result shows that the environment is correct.