The Research Of Time Delay Estimation Algorithm In Digital Predistortion System

Reducing power amplifier’s output power is the simplest way to improve thelinearity of it, so the device is operated in its linear region (back-off technology).Though this approach is simple and valid, it severely degrades the power efficiency.Compared with the back-off technology, feed-forward technology and feed-backtechnology etc, the digital predistortion technology based on memory polynomial modelhas advantages of high adaptability, low cost, wide band and high dynamic range. Atpresent, it has become one of the cost-effective way to improve the linearity of PAs.Because time delay estimation error may decrease the performance of predistortion fordigital predistortion system, Then the loop delay between input signal and the feed-backsignals must be controlled precisely so that the convergence of the predistortionalgorithm can be assuredIn this paper, the theoretical parts combined with measurement results wereexplained. Firstly, the nonlinearity features of PAs were introduced in detail. Then theinfluences of PA’s nonlinearity to constellation and power spectrum were also analysed.Whereafter, the relationship between PA model and predistorter model was inferred atfull length. Then we demonstrated and analysed particularly how the peak power andaverage power of input signal affect the PA model, and how the predistorter affectes thepeak-to-average ratio of input signal.In this work, the algorithm of extracting predistortion parameter was expounded,and this algorithm was based on QRD-LS and used Givens rotation to realize QRdecomposition. Simultaneously, some Matlab codes were also provided for reference.On the the basis of other researchers, a improved algorithm of time delay estimationwhich is ground on cross correlation function was also presented. By adding thealgorithm of max value finding and combing with using the digital differentiator, it cannot only decreases the computation largely, but also improves the precision of thenumeration. In the first stage, we simulated the algorithm by Matlab, Then transformedit as Verilog language and Designed it with the ISE which is the exploitation tool ofFPGA. Lastly, we validated the algorithm successfully with Modelsim. At the same time, the Matlab codes of time delay estimation algorithm were afforded. Likewise, theideas and methods of algorithm’s FPGA accomplishing were also offered.In this work, Finally, the compostion of the base-band digital predistortion systemand it’s principium were introduced deeply, then the three hardware modules:FPGAdevelopment kit, analog up conversion, analog down conversion and Dorhety PAmodule were introduced. Meanwhile, the design of key technologies were elaborated indetail, such as the generating of LTE signal, digital up conversion, digital downconversion, the sampling and storaging and reading of the signal. Simultaneously, thekey of the design was pointed. After accomplishing the feasibility verification of thetime delay estimation algorithm, this algorithm was put into the digital predistortionsystem for testing, and the measurement results show that, for the LTE signals whichhas5MHz bandwides, the ACPR of PA up channel and down channel output signalwhen use the digital predistortion technology are improved13.47dBc and12.91dBccompared with not use it.