The Asic Design Of Coding And Error Correction Circuit For10G EPON

As the increasing of the operations of broad band, Optical fiber communicationsdevelop very fast.10G EPON becomes the main technology of optical fiber commun-ications for the advantage of widder bandwidth and the perfect compatibility withEPON. Nowadays, more and more college, corporation and research organization makethe research on10G EPON. But only the company from abroad could design10GEPON chip. So design the10G EPON chip by ourselves could remove the rely on theforeign company. This paper makes the research on the coding and error correctioncircuit for10G EPON, which is the critical part of10G EPON physical layer. Datacommunication rely on coding and error correction, and coding and error correction isthe main reason for chip area. So it is valuable for researching the coding and errorcorrection for10G EPON.The main work of this paper is:(1) At the beginning of design, research the protocal deeply, including802.3and802.3av. Understand the function of each sublayer in10G EPON physical layer, and setthe framework of the design.(2) Base on the understanding of the protocal, choose the right arithmetic for codingand error correction. Thereinto, two common coding methods are8/10B and64/66B.This paper analyzes and compares the theory of two methods. Besides, the choice of thearithmetic of error correction is the key of the design. In chapter3, analyzes deeply andputs forward one modified arithmetic. This arithmetic could correct the errors in10GEPON, and it needs less chip area, so it is adapt for10G EPON.(3) After choosing the arithmetic, design the circuit of coding and error correctionand verify the circuit on FPGA. The design is divide into sending and receiving parts.Sending part includes64/66B encoding, scramble and RS encoding. Receiving partincludes RS decoding, descramble and decoding. After finishing the design, verify thedesign on FPGA.(4) Do the logic synthesis for the circuit of coding and error correction after passthe simulation and verification of the function. Logic synthesis is the bridge betweenfront and backend design.It is the key for the realizability of the back design. (5) implementing coding and error correction circuit. After the logic synthesis,could get the synthesis netlist and the document of timing restrict. Using these, could dothe backend design, such as plan and route, formality,STAand so on.