Optimization Policy For Multi-level Cell STT-RAM Based Cache

Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. While the traditional multi-level SRAM-based cache hierarchies, especially in the context of chip multiprocessors (CMPs), present many challenges in area requirements, core-to-cache balance, power consumption, and design complexity. The emerging Spin Torque Transfer memory (STT-RAM) is a promising candidate for future on-chip caches due to STT-RAM’s high density, low leakage, long endurance and high access speed. However, one of the major challenges of STT-RAM is its high write current, which is disadvantageous when used as an on-chip cache since the dynamic power generated is too high.According to the characteristics of the multi-level cell (MLC) STT-RAM, we propose dynamic encoding policy to reduce the write energy of MLC STT-RAM. Each cell of MLC STT-RAM has four resistance states-R00, R01, R10and R11. The four resistance states have different write energy. And through the statistics we found that the proportion of the data (00,01,10and11) which written into L2Cache are change with time and applications. Therefore, we propose to change the map between the four resistance states and the four two-digits data dynamically according to the proportion of the data, the resistance state which has lower write energy can represent the two-digital data which appeared more frequent.In this article, we propose phase based dynamic encoding policy (PBDE) and application based dynamic encoding policy (ABDE). The PBDE divides the procedure into many phases, and each phase can choose a best encoding scheme. The ABDE choose the best encoding scheme of cache blocks according to the application. Our experimental results show that the PBDE and ABDE can achieve2.7%and4.5%write energy reduction respectively.This article also improves the replacement policy of multiprocessor shared STT-RAM based cache. As the experiment data depicted that the replacement between the blocks which belong to the same application has more same data than the replacement between the blocks which belong to the different applications. Under the read before write policy, if there are more same data between the replaced cache block, the write operations will reduce. Therefore, we propose an improved cache replacement policy for multiprocessor shared STT-RAM based cache. The improved cache replacement policy discovers the unused block by prediction policy and enhances the opportunity of cache replacement between the same application’s block without miss rate rise. The evaluation shows that the improved replacement reduces5.4%write energy and achieves1.5%performance improvement.In summary, this article optimizes the write energy and the write number of multiprocessor shared MLC STT-RAM based cache by dynamic encoding policy and improved cache replacement policy. As the experiment results shown, those policies achieve write energy reduction for most benchmarks.