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Interfacial Stress Analysis Of Through Silicon Via

Posted on:2014-11-17Degree:MasterType:Thesis
Country:ChinaCandidate:W LiFull Text:PDF
GTID:2268330392973523Subject:Solid mechanics
Abstract/Summary:PDF Full Text Request
As one of the two key technologies in the electronics field, Electronic Packagingplays an important role in the reliability, electrical properties, thermal properties andminiaturization of the integrated circuit. Currently,3D packaging is considered to bethe mainstream of the development direction of future packaging technology. In3Dintegration technology, TSV (Through Silicon Via) technology plays a very importantrole in achieving the shortest, the most abundant in z direction interconnect, TSV hasbecome the most promising packaging technology.TSV is a key technology for3D integration, which is by making through hole inthe z direction on a silicon wafer, then filling a conductive material inside the hole toachieve the interconnection between different chips. Currently, TSV’s basicconfiguration includes: Cu through-hole, SiO2insulating layer, Ta barrier layer, Siwafer. When the TSV structure bears different process temperature loads, thestructure will generate a great thermal stress because of the big mismatch of CTEbetween different materials. The great heat stress results in the cracking of TSVinterfaces, leading to the failings of TSV. Scallop shape of the TSV interfaceexacerbates the interface failures.In this paper, three interfaces (Cu/Ta、Ta/SiO2、SiO2/Si) of TSV are considered.There are two interface contact forms of TSV interfaces, one is fully bonded interfaceand another is interfacial sliding model. In the fully bonded interface model, theinterface is regarded as the ideal one, when the interfacial stress reaches the criticalvalue, the interface starts to break. In the interfacial sliding model, when theinterfacial shear stress reaches the yield stress, the shear stress remains constant, theinterface still bonded but the copper will rise/indent on the silicon surface.We extract the interfacial normal stress and shear stress under the fully bondedmodel. Also we analyze the impact of geometric size factor (the diameter of via, thethickness of the Ta layer, the roughness factor λ, h) for interfacial stresses. Themaximum interfacial stress occurs at the first scallop of the through-hole entrance;geometric size factor has a greater impact on interfacial normal stress, but the impacton the shear stress is negligible; the maximum interfacial normal stress increases withthe diameter of the through-hole; when the Ta layer thickness increases, the maximumnormal stress of Cu/Ta、SiO2/Si interfaces decreases but the stress of Ta/SiO2 increases; with the roughness factor h increasing, the interfacial stress curve becomesteepened and the maximum interfacial normal stress increases; the roughness factor λplays the opposite effect on the interfacial stress; when the h and λ meet thecondition of (μm)16.7h(μm)0.22, all the interfacial normal stress of scallopinterface is compressive, which means the interfaces of Cu/Ta、Ta/SiO2will not havecracking damage.In the interfacial sliding model, the amount of copper protrusion becomes theevaluation criterion of TSV reliability. Ta layer thickness has little effect on theamount of copper protrusion, the diameter of through-hole and λ are up to the amountof copper protrusion and h is inversely proportional to the amount.
Keywords/Search Tags:electronic package, TSV, scallop shape, interfacial stress
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