Research And Implementation Of FPGA-based JPEG2000Image Compression System

Digital images have been used widely in modern society nowadays. Because ofthe huge size of the raw image format,much importance has been attached to theJPEG2000. Although JPEG2000has been determined at the end of2000,thetechnology can not be recognized in computer networks,wireless communications andother practical applications. Its function has to be further strengthened. Standardsadopt the Discrete Wavelet Transform (DWT) and Embedded Block Coding withOptimized Truncation (EBCOT),which include a large number of time-consumingand complex algorithms,therefore new requirements are needed in order to improvethe encoding speed and meet the real-time applications.This paper researches on the first part of JPEG2000standard，analyses theJPEG2000coding system for each coding module,study and optimize the corealgorithm of discrete wavelet transform,bit plane coding and arithmetic coding. Inreal-time image coding system,the wavelet transform as a result of the calculation of alarger volume requires a large amount of storage space. It is not conducive to high-speed and low power requirements of the hardware implementation.So the hardwarearchitecture of two-dimensional5/3wavelet transform based on a pipelinedprocessing is designed in this paper. The architecture adopted the periodic symmetricextending approach to restrain discontinuity of the edge of the signal and ensure thenormal operation of the pipeline by adding the buffer module between row transformand column transform. The use of multiple data parallel input mode scheduling hasgreatly inereased the processing speed of the module.EBCOT algorithm is the most complex one in the entire system of JPEG2000.The part of the processing time is usually more than50%in the core of the JPEG2000algorithm. Therefore,EBCOT algorithm becomes the difficulty of JPEG2000 compression system design.To solve this problem,the bit-plane encoder VLSIstructure based on three parallel processing is designed,the way of encoding all thedata in a bit-plane during a clock cycle is proposed Which greatly enhanced the speedof the encoding. As for the VLSI implementation of binary arithmetic codec,thebinary arithmetic codec based on three-pipeline architecture is presented,whichreduces the coding complexity, assigns work process of each module and improve theencoding speed.The three proposed architecture is implemented by Verilog HDL at the end of thepaper. The result of simulation and synthesis proves the correctness of the design.