Ring-based Network-on-Chip Architecture Design And Performance Evaluation

With the continuous increase of parallel computing complexity and rapid growth of on-chip IP (Intellectual Property)’s number, the System on a Chip (SoC, System-on-Chip) could be designed for much more complicated and high performance needed jobs. But the continuous decrease of the process dimension and the rising demand from practical application on the performance make the traditional bus based on-chip communication architecture face enormous challenges. Emerging on-chip communication technology:Network-on-Chip (NoC) uses its powerful parallel processing ability, agile and scalable communication structure characteristics to replace the traditional bus-based communication architecture. NoC has become the hot spot of chip system communication architecture research.This paper has the research object which is the NoC communication architecture based on the ring topology. This paper researches on the structure design, modeling and simulation method, and the performance evaluation technology. Two ring topology structure based new NoC communication architecture are designed central controller based NoC and virtual channel based polycyclic NoC. This paper systematically describes the above two kind of new NoC architecture’s design process, the core module structure design method and communication mechanism design and optimization method. This paper uses two different abstract levels (register transfer level, network level) to do the establishment of simulation model and performance evaluation, and then analyzes the advantages and disadvantages respectively in communication performance.Network-on-chip has diversified topology structure, complicated communication protocol and many configuration parameters, which constitute a huge design space. How to choose the most suitable structure is one of the important problems to solve during the early design. This paper puts forward a kind of high-level cycle accurate NoC communication architecture performance evaluation simulation platform, systematically describes the high-level NoC simulation model building method. It supports two kinds of topological structure (grid and ring) of the NoC simulation, overcome the limitation of the traditional single topological structure. The transaction level modeling and high-level abstract software method improve the simulation efficiency and ensure the reliability of the evaluation simulation at the same time. This paper expands the virtual channel technology facing the router structure, and supports various numbers and depths of the virtual channel configurations, and broadens the explore space for designers. And, this simulation platform supports user-defined structure, which is suitable for large-scale NoC design space exploration and structure parameters optimization. Benefited from the NoC high-level performance evaluation simulation platform, NoC architecture design and optimization and performance evaluation efficiency were significantly improved.