Implementation And Verification Of The E1overIP Circuit Emulation Adapter

With the worldwide surge in data flux and the development of network technology, various techniques based on IP will likely become the main technologies for future information communications. So the main research direction for the development of the next generation communication is to build a new network, which can provide integrated services for voice, data and video etc and achieve the transition and transformation from circuit switching to packet switching.The technology of TDMoIP offers technical support practically for this transformation. It connects IP network and traditional TDM network seamlessly to bear TDM business in a simple way.In this thesis, basic concepts and technical points of TDMoIP technology are introduced. We principally analyze some key aspects such as packet encapsulation, packet loss and disorder, clock recovery and the design of dithering buffer etc. As an application of TDMoIP technology, the design of EloverIP circuit emulation adapter system and implementation of the functional modules in the research project are completed. The design mainly describes the key modules such as the clock recovery module, the queue management module and the network timing delay absorbing module. The clock recovery module can recover the accurate original clock with the help of digital PLL technology. The queue management module can realize the packet loss and the disorder process. The network timing delay absorbing module is realized with the use of dithering buffer. Functional modules introduced above have been implemented by Verilog HDL. And adapter solution is timing simulated by the tool of Modelsim whose copyright is Mentor Graphics corporation. Finally, by designing environment module, we simulate the real network environment, which may contain packet timing delay, loss and disorder. For a variety of board-level functional testing, it shows that the E1overIP circuit emulation adapters can achieve the desired objectives.