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Design And Implementation Of Key Technologies For Data Push-Pull Bus Protocol On Multi-core Network Processor

Posted on:2013-06-19Degree:MasterType:Thesis
Country:ChinaCandidate:W B MaFull Text:PDF
GTID:2248330395956722Subject:Microelectronics and Solid State Electronics
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With the rapid growth of the Internet and the rapid development ofmicroelectronics technology, the network processor which is the core equipment ofmodern network system is evolving toward multi-core SoC. Because of it’s highflexibility and efficient function of parallel processing, Multi-threaded Data ProcessingUnits have been widely welcomed. Their special characteristics make them even moreease when they have to deal with the frequent updates of network protocols and rapidincrease in network bandwidth. As one of the key structures of network processor, businterface unit takes a lot of tasks which are associated with data path and control path,and the effectiveness of its design greatly influences the performance of the networkprocessor system. Since the core structure of bus interface unit is push/pull engine, howto achieve its function became the key points of network processor system.In this dissertation,a on-chip program is designed for multi-threaded andmulti-core packet processor,which is mainly for the multi-thread packet processorarchitecture of XDNP multi-core network processor.It focuses on the protocol designand specific hardware implementations of data push-pull program which are based onthe storage controller.In the dissertation, the technical details such as ready-pollingmechanism, port contention resolution, buffering storage design and Direct MemoryAccess have been studied and the design details such as task execution order andinstruction distinguish mechanism have been described, which are all associated withpush/pull engine. By the design of the control state machine and instructionidentification mechanism of push-pull engine,the function of data push and pull enginehave been well implemented.Then,a complete asynchronous data access mechanism formulti-threaded processor is presented out. Finally, based on random stimulus generationmechanism and the assertion verification method, a detailed functional verification hasbeen taken for the push-pull engine interface module. And on this basis,the functionalverification and analysis for the data transmission process of the entire system-on-chiphave been completed.The results prove that the design of the interface module meetsthe design requirements of the system.
Keywords/Search Tags:Network Processor, Bus Interface, Push/Pull Engine, FunctionalVerification
PDF Full Text Request
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