Study On Multi-Level/Multi-Bit Techonology In Nano-size SONOS Device

Polycrystalline Silicon-Oxide-Nitride-Oxide Silicon (SONOS) gets much more attention for good retention properties, low cost and easy scalability. In particular, it can realize multi-bit and multi-level cell programming simultaneously, significantly increasing the memory storage capacity, so it may become a competitive candidates to replace the traditional floating gate flash memory in the future.However, as the cell channel length is scaled down to nano-meter size, SONOS is confronted with a lot of problems. The mismatching between injeced electrons and holes during programming and erasingresult in a big upward drift of threshold voltage (Vth) window and more serious second bit effect. As a result, the cycling endurance is seriously degraded, especially in the multi-bit/level cell.In order to study these problems and realize high density storage with the multi-bit and multi-level technology in90nm SONOS meomory, we compare several different programming mechanisms, the traditional channel hot electron injection (CHEI), the channel hot electron injection with a positive substrate bias (CHEI-P) and pulse agitated substrate hot electron injection (PASHEI).Several measurements such as charge pumping and reverse read are used to characterize the distribution of the charge.During the cycling, both PASHEI and CHE-P programming show improvement and the later gets the least Vth shift by suppressing the secondary electron injecting (SEI) to improve the mismatch between electrons and holes. The improved endurance is due to the less accumulation of charges in the nitride layer, evidenced by charge pumping technique. CHEI-P also gets good endurance in the two physical bits by suppressing the secondary electron injecting (SEI). The much narrower electron injecting region not only improves the mismatching between the electron and hole during the programming and erase, but also suppresses the secondary bit effect. And so CHEI-P exhibits the superior endurance and retention properties after104program/erase cyclings in4-bit/4-level programming operations. Meanwhile, CHE-P is completely compatible with the incremental step pulse programming(ISPP) technique, and the forward-biasing between the source and substrate junction greatly reduces the power consume.In order to inversigate the main loss mechanism during the rentention, we compare the retention of these samples with three different programming methods. Due to the different charge profile in the storage layer, if the charge lateral redistribution plays the important role in the retention the threshold voltage lossin the programmed state will be apparent. However, they almost show the same Vth loss. And the CP measurements between0s and50K s performed on different samples after10k cycles have no obviously shift. Above experiments all reflect that the vertical loss model plays the most important role during the degradation of retention at room temperature, rather than the lateral redistribution model.