Software Design Of Video Surveillance Server Based On Tilera Multi-Core Processor

In recent years, with the rapid development of economy, the demand for video surveillance is growing fast. Video surveillance systems are becoming more and more widely used in various fields. Video surveillance server is the core unit of the whole network video surveillance system which is used to manage front-end monitoring terminals, to response to users’request, and to display local video. Traditional video surveillance servers are designed to work on PC, which bears low system integration, high cost and poor stability. Therefore the development of stable and low-cost video surveillance server has high engineering applications significance.This thesis designed and implemented a video surveillance server based on Tilera multi-core processor. The software design of the video surveillance server is based on modular theory, which can be divided into three modules:transaction center, database module and local display module. Transaction center is mainly used to manage front-end monitoring terminals and to response to users’requests with thread pool, so it cans response to requests parallel and efficiently. The database module stores the whole data of the system and provides reading and writing access interface to the transaction center. The server uses high-density and non-volatile flash memory as its storage media. To solve the problem that current flash-based database index mechanisms don’t have both high update and query performance, this thesis proposed an efficient database indexing mechanism, which updates the index through log method to ensure highly efficient update performance. Meanwhile by using node-log map table and integrating node loges, this indexing mechanism can ensure query performance. Finally with multi-core resource, the server achieved local multiple HD video display. The local HD video display was fulfilled by Tilera processor and FPGA, which were connected by PCIE bus. And the Tilera multi-core processor was responsible for receiving and decoding of the video stream. Then it transferred the decoded video stream to FPGA for display by DMA. The DMA satisfied the requests of the data transmission speed and the bandwidth for the multi-channel HD video display.