The Design And Implementation Of Large-capacity Cache Compression Device

In the field of aerospace, compression is one of the main measures to solve the pressureof massive data that bring to the limited channel bandwidth. Remote sensing images areparticularly precious because of the acquisition price is so high, but also bring a hugechallenge to the compression technology. How to improve the compression ratio, and ensurea few difference between the restored image and the original image is the main developmentgoal of the current compression techniques. At present, the JPEG2000standard solve theexisting contradictions very well. In order to meet the requirement of real-time data in thespecial field, the design of the large-capacity cache FIFO is also a hot research direction.This paper introduces the development status and application fields of the data cache andcompression firstly. According to the demands, we decide to use Cyclone II series FPGA ofAltera company as the logic control chip, two pieces of SDRAM to cache the data ofping-pong structure, and also use JPEG2000chip ADV212of ADI company to compressdata. This paper introduces the structure of each function unit and the operation principle ofthe large-capacity cache and data compression. In order to reduce the complexity ofprogramming, we use the simplified FSM of SDRAM. This paper apply in the dual-portRAM IP core in Quartus to configurate ADV212firmware, greatly simplify the designdifficulty of the VHDL program. In order to ensure the reliability of SDRAM, the designadopts the equal length of routing in PCB, and connect33Ωresistor to the main control signalto eliminate interference.At the end of the paper, we test the function each of module, and also analyze the dataread from cache chip, restore the compressed data. The results show that the cachecompression device can meet the requirements, but also have an important practicalsignificance.