Digital Baseband Design For UHF RFID Reader And Cyclic Redundancy Check Arithmetic Research

Radio-frequency identification (RFID) is a new technology of non-contact automatic identification which can capture information accurately and flexibly by using wireless channel. And UHF frequency-band possesses many advantages, such as long-distance, fast reading speed, low operation cost. So much attention has been paid to the UHF frequency-band RFID systems.RFID reader consists of Mico control unit, digital baseband part and radio frequency part. The digital baseband plays a key role in the design of the RFID reader. So there are two important considerations before the design. First is how to design the architecture of digital baseband based on the protocol. The second is whether the design of digital baseband can control the reader effectively, and make it know when and how to transmit data to tags and receive the backscattered data. In addition, there is Cyclic Redundancy Code (CRC) problem in UHF RFID system, which affects the normal operation of the whole identification system. Therefore, in this paper, a new CRC algorithm that performs CRC computation in parallel has been proposed. Based on the reading and analyzing of related literature. The main work and innovation are as follows:(1) A digital baseband system for UHF RFID reader based on ISO/IEC18000-6B protocol has been designed. Based on deeply research on ISO/IEC8000-6B protocol, the digital baseband system consists of two parts:transmitter and receiver, which including frame header processing module, Manchester encoding module, FMO decoding module, CRC16check module, control module, data processing module, anti-collision module. It is described in verilog HDL in RTL level, and simulated by Modelsim with the use of testbench, with Synplify for synthesizing and Quartus Ⅱ for function simulation. FPGA proved it can work properly in the specified clock frequency based on the protocol.(2) A new cyclic redundancy check (CRC) algorithm that performs CRC computation in parallel based on Mcu control has been proposed. The heuristic algorithm is focused on minimizing memory space and implementing easily. The results are combined together by XOR operations. A16-bit CRC algorithm is described in assemble program, called by8051IP core, with Synplify for synthesizing and Quartus II for function simulation. The simulation results show that our proposed CRC algorithm can work properly in the specified clock frequency.