Research On Pattern Grouping And Pattern Selection Methods For Small-Delay Test

With the development of the design of integrated circuits (ICs) technology, thedensity of integration is improving, and the clock frequency is speeding up, thetesting becomes more and more difficult, and it has been one of the biggest challengeson semiconductor industry. New materials and new technology easily cause thephenomenon such as the power supply noise, crosstalk effect, process variation,resistance open and short and so on, leading to a large number of small-delay defects,so it is very important to check these defects to make sure the dependability of thecircuits. The detection of small-delay defects mainly depends on the quality of the testset, so the test generation of small-delay defects becomes a hotspot in the field ofdelay test. This thesis focuses on the test generation of small-delay defects, and putsforward two kinds of optimization method about the quality of the test set and data oftest generation. Several ISCAS’85and ISCAS’89benchmark circuits have beenutilized to verify these methods. The main content of the thesis includes:Firstly, this thesis proposes a method of self adjusting test pattern grouping onfaster-than-at-speed. The method of faster-than-at-speed could detect small-delaydefects effectively, but the grain size of pattern grouping is too thin, which will causeserious overtesting. The proposed method aims at overtesting avoiding. It uses thefault simulation and static timing analysis technology to evaluate overtesting and testescape phenomenon. Then it regulates test clock according to their respectivesituation, thus the result of pattern grouping is changed. The method makes use of thetest vectors to simulate, which is got after test clock adjustment, then evaluates thereduction percentage of overtesting phenomenon. Ultimately, the experimental resultson ISCAS’89benchmark circuits show that the proposed method could significantlyreduce overtesting, which is up to39.30%.Secondly, this thesis puts forward a method of the test vector screening onsmall-delay defects. To simplify small-delay test process and reduce test cost, thepaper proposes a new small-delay pattern selection method which regroups testpatterns of stuck-at faults to detect small-delay faults, and then selects patterns thatcan effectively detect small-delay faults. Ultimately, only by using this optimizingtest set, the stuck-at faults, transition faults and small-delay faults can all beeffectively detected. The experimental results on ISCAS’85and ISCAS’89benchmarkcircuits show that the proposed pattern selection method in this paper produces a test set of high small-delay faults coverage and reduces test data volume.