Study On MOS-Type Devices On SOI Substrare With Low On-State Resistance For Lateral High Voltage Applications

With the development of SOI (Silicon On Insulator) technology, SOI HVIC (High Voltage Integrated Circuit) becomes mainstream and trend of the PIC (Power Integrated Circuit) due to its improved isolation, reduced leakage current, elevated speed performance, improved high-temperature performance and perfect irradiation hardness. MOS-based power device grows as the dominant product due to its good gate control capability and simple drive circuit, instead of power BJT and thyristor. As one of the key device in SOI HVIC, SOI lateral power device has been paied much attentain by researchers in this field. The breakdown voltage and on-state resistance are the important characteristics which are used to measure a lateral power device. How to realize a SOI lateral power MOS-based device with high breakdown and low on-resistance has great significance to the development of PIC.The researches and peogress recently on SOI lateral power device were outlined in this paper. The design principles and methods of the of SOI lateral power device were summarized, as well as, the on-state resistance characteristics of SOI LDMOS and SOI LIGBT were modeled and analyzed. Forward block characteristics and on-state characteristics of SOI LDMOS and SOI LIGBT were simulated by SILVACO TCAD. Better device performance was obtained by optimizing parameters of device. Through this course, two problems were found:one is that vertical channel SOI LDMOS had a high resistance of its parasitic JFET region although the vertical gate structure could be easily achieved with good deep trench prccess of rapidly developing CMOS technology; the other is that vertical breakdown voltage of SOI high-voltage devices was low because substrate does not participate in standing vertical voltage, the breakdown voltage is determined by the smaller one of the lateral and vertial breakdown voltages, which made it difficult to realize SOI high-voltage devices with its breakdown voltage over800V. Then, in this paper, two novel structures were proposed to solve the two problems above respectively.One novelly proposed structure is SOI LDMOS with Double Trench Gate (DTG) in order to optimize the on-state resistance characteristic of vertical channel SOI LDMOS. The DTG SOI LDMOS is obtained by introducing an additional trench gate between P-well region and N-drift region, which can form one more n-channel in on-state. The parameters obtain through2D device simulation with SILVACO TCAD are analyzed. The simulation results indicate that the propsed DTG SOI LDMOS is featured of lower on-resistance. Morever, the breakdown voltage and tansconductance of the proposed device was also improved. Meanwhile, the feasibility of the proposed DTG SOI LDMOS in standard CMOS technology was researched by process simulation with SILVACO TCAD ATHENA. The other novelly proposed structure is SOI lateral high-voltage structure with a buried P-type layer (BPL) in order to elevate the vertical breakdown voltage of SOI lateral high-voltage structure. The proposed BPL SOI high-voltage devices structure consist an additional buried P-type layer which is inserted between BOX layer and SOI layer based on the conventional SOI high-voltage device structures. When the device is biasd in forward block state, the junction across the interfance between N-drift region and the buried P-type layer is reversely biased, which bears the most part of the vertical forward voltage drop instead of thick BOX layer. The forward block and on-state parameters of BPL SOI LDMOS and BPL SOI LIGBT obtained through2D device simulation with SILVACO TCAD are analyzed. It was proved that the proposed BPL SOI high-voltage structure can not only elevate its breakdown voltage up to1400V with appropriate parameters, but also improve its thermal propenties significantly by reducing the thickness of BOX layer down to a few hundreds of nanometers or even less. A part of on-state current flows from drian to source through the buried P-type layer in BPL SOI LDMOS, which makes inner on-state power consumption lower because of bigger on-state current cross-section. At the end, SOI-based substrate material with buried P-type layer was designed, on which BPL SOI lateral high-voltage device structures could be fabricated.