Power Detection Circuit Design

In order to expand received signal dynamic range, automatic gain control modules are widely integrated in modern digital TV tuners. Because of the advantages of not introducing additional noise and flexible control algorithm, the programmable automatic gain control (PGC) is getting more and more research and application.The main work of this dissertation is design an intermediate frequency received signal strength indicator (RSSI) and a radio frequency power detector (PWD), applying to PGC in the tuner with zero IF architecture.First, the basic knowledge of PGC is introduced briefly, and an overview of a PGC scheme applying to a zero IF receiver is also introduced. The performance parameters of RSSI and PWD are given in terms of the PGC application.Second, the design of RSSI is presented. The principle of successive detection architecture is reviewed; output errors of the amplifier and rectifier are discussed in detail. According to the theoretical analysis, compensation circuits are designed and the performance of device match is also optimized. In this design, the slop of RSSI is38.8mV/dBm, the settle time is130μs, detection range is-20dBm～+3dBm, the effective frequency range can reach20MHz, the power is2mW.Finally, the design of power detector circuit is introduced. A single ended digital control power detection structure is used. The principle of this architecture, frequency characteristics and detection error is analyzed. The bisection technique is used to calibrate output DC offset. In this work, the frequency band is50-860MHz with-26dBm～-14dBm detection range, the settle time is100μs, the total power is3.8mW.All the circuits in this work are designed and simulated in a TSMC0.18-μm CMOS process.