Research On Metal Line Void In55NM Technology Back-End Process Integration

Metal hard mask Dual Damascus All in One integration process hasbeen widely used in55nm IC manufacturing process, which solves thecorner rounding on top of low-K dielectric, thinner thickness of low-Kbetween trenches and smaller sidewall angle issue with the traditional DualDamascene process, but there are also some new accompanying issues anddefects, such as the metal void found in the technology developmentprocess. This metal void will cause larger metal line sheet resistance toincrease the capacity resistance delay during signal transmission in metallines and block the signal transmission, which will result in metal line openin worst cases to cutoff the signal transmission. At the same time, the metalline void will cause serious reliability problems, such as stress migrationand electromigration.In this paper, the occurrence condition of metal line void as well asthe defect evolution process was summerized through the investigation ofenvironmental factors defect generated and defect step by step check, androot cause of metal line void was specified. The stress of metal hard maskmakes the bending of dielectric layer and smaller trench opening betweenmetal lines, which caused the result that copper cannot be deposited intotrench to form void in copper electroplating deposition process.Three process modification methods were proposed to eliminate themetal line void, that is, the litho pattern size adjustment, zero-bias etchingand reducing the metal hard mask stress, among which reducing the metalhard mask stress process is the most direct and effective.