Digital Satellite Broadcasting System And The Receiver Logic Module

The advent of television, so that people’s cultural life more colorful, constantlyenrich the rapid development of science and technology and the social and material,people’s requirements on the television program are becoming higher up. Digitalcompression technology matures, the television images, audio digital transmission isno longer an ideal to become reality. Of TV programs using digital technology, thetransmission loss is small, the image interference is small, and almost no noise, noghosting advantages of program effects has greatly improved image qualitycompared to analog transmission, and transmission of digital signals requiredchannel bandwidth is also greatly reduced, the channel bandwidth for thetransmission of an analog TV programs, you can transfer multiple sets of digitalprogramming, so that a significant reduction in transmission cost and the satellitechannel resources. Due to the needs of specific situations, the signal format is notlimited to the traditional television signal transmission; there has been such as ASI(Asynchronous Serial Interface) signals and SDI (serial digital component) signal.Because of the bit rate of these signals are usually larger, therefore, when receivingsuch signals, we need to do some processing.Designed several FPGA-based signal processing method to solve the overflowof the ASI signal frequency output SDI signal embedded audio and other issues.First, the in-depth study of the basic rationale of the digital satellite receiver:the modulation of digital signals; the structure of the SDI and ASI signals; theformation of the TS stream as well as identifying the role; the principle of the audioembedded in the SDI signal; asynchronous serial signal transfer theory.Second, the logic of the digital satellite receiver module design: buffer moduleof ASI, SDI audio embedded module analyzes the feasibility, and the buffer modulealgorithm improvements to enable them to receive high bit-rate signal.Last, through VerilogHDL language, call the system comes with IP core toachieve the corresponding functions in the FPGA, and gives the RTL view and theexternal interface, then through the Quartus software comes the signaltap ofdebugging tools for online simulation, and analysis of the results is given...