USB2.0Physical Layer Interface Chip Digital Design And Chip Verification

With the rapid development of domestic computer technology, consumers increasingly high requirements on the external bus speed, the applications of high-speed busess are more and more wide. In this environment, the USB device has been rapid development, from the initial version of USB1.0to USB2.0version, data rates become faster and faster. At present, the USB2.0bus owns the features of easy use,high speed,interface-supplied power,hot plug,good compatibility,low power and so on.These features make it to the interconnection standards of the PC and the mobile devices.USB2.0PHY (physical layer) has a strong versatility as an indispensable part of USB2.0devices, either as a separate chip in the USB system, they can be used as IP cores, integrated directly into the large to SOC design.And it will have wide market and practical applications.In this paper, is based on the requirements of the agreement of the UTMI (USB2.0Transceiver Macrocell Interfaces), USB2.0PHY division of the overall structure and its functional modules. The structure is divided into three parts:the analog to send the front-end, PLL, and digital control circuits. The paper elaborated on the register configuration of the digital control circuit module, and send data to the control logic state machine, the NRZI module, bit stuffing module, parallel to serial module implementation of principles and methods. Complete the design and integration of other modules, the USB PHY module rigorous digital logic simulation, and analysis the simulation results. USB PHY design tapeout after SMIC’s55nm process, for the of the chips detailed chip verification, Verification is divided into three parts:The first part is to verify signal integrity for chip, Oscilloscopes with the USB compliance test software, the USB PHY chip eye diagram validation, By comparison of the failure of the eye diagram and the success of the eye diagram, thus proving the chip signal integrity test; The second part is the basic interface control signal timing for the digital circuit verification, crawl through the oscilloscope signal phase relationship, in order to carry out the verification of timing; The third part of the internal digital logic circuit for this design verification, integrated test system in the FPGA development board, two USB PHY test daughter board to receive and send data, Automatic comparison module in the test system, send and receive data comparison, in order to achieve the completion of the purpose of verification of digital logic circuits of the chip. The paper concludes with a summary of this study work, and some of the future need for further improvement in this subject.