The Research Of The Communication Of The Absolute Magnetic Encoder

The servo control system is an active research topic in Mechanical and electrical technology for the stability, high accuracy and fast response. High-speed and high-precision are becoming the trend of the development of servo drive systems, which are partially decided by the position detector. Magnetic encoder is more suitable for high-speed, high-precision servo control system due to its simple structure, easy implementment small and the ability to adapt harsh environment. But there are still significant limitations of magnetic encoder. On the one hand the domestic industrialization of magnetic encoder is immature, and the precision is poor, which can not meet the requirement of market. On the other hand, the performance of foreign product is good, but the communication interface between the controller and the encoder is controlled by the corresponding communication protocol, and the protocol is controlled by the special chip, which accounted for more than a quarter of total costs. The purpose of this thesis is to improve the accuracy of magnetic encoder and design the communication interface. The main work of this thesis can be summarized as follows:Firstly, this thesis focuses on the signal processing of magnetic encoder. On the side of signal processing part, this thesis analyses the disadvantage of conventional arctangent processing method, then choose the arithmetic that based on look-up table, the angle was got through the table look-up in different regions according to the3-phase voltage. By using this method, the magnetic encoder’s precision has been improved and the computation of the processing has been reduced, at the same time realizing the high calculating speed and real-time signal processing.Secondly, when we design the interface between the controller and the magnetic encoder, because the magnetic encoder’s accuracy is high and the median is excessive, we always use the serial communication. This thesis uses the UART serial data transfer protocol, include the transmit module, receiver module and the baud rate generator module.Finally, this thesis uses the Verilog HDL to integrate UART central function into FPGA which can make the whole design tighter, steadier and more reliable. This thesis is based on FPGA component to implement UART, and CRC is used. Program can be simulated to function and timing by ModelSim, to validate whether the design can gain expected function and the design program can run normally when it is downloaded into logical chip.