Design Of Displaying System And Image Preprocessing Based On FPGA

The important part of image preprocessing is image acquisition. The speed ofimage acquisition and the quality of image will directly affect the result of thesubsequent treatment. Large volume of data, real-time requirement, and relativelysimple operation are main features of the image acquisition system. FPGA has thesignificant advantage in the speed of data processing, so it is very suitable for imageacquisition system. In recent years, with increasing development of the VLSImanufacturing technology and computer technology, especially the rapid developmentof the programmable logic devices FPGA and the memory modules, making the speedof the video image capture has been greatly improved.In this thesis, the image acquisition system is explained in detail, and the relevantprinciple of the image capture is described. Then a systematic design of the imageacquisition based on FPGA is presented. The XC4VSX25chip of Virtex4family ofXilinx’s FPGA is a kernel device in this system. The external TVP5150that islaunched by TI company as the video decoder for decoding the image data of thecamera captured into a standard video data ITU-R BT.656. DDR SDRAM is used asimage storage, which can store two-dimensional image data quickly and effectively.And the digital-analog converter chip ADV7123is used to convert the digital data toanalog signal for displaying.Peripheries of the chips are connected to the core chip of the system FPGA, andthe control of the various parts of the system through the control module which isdesigned in FPGA. FPGA initializes the TVP5150by configuring the relevant registerthrough theI~2C bus, and theI~2C control module is designed in FPGA. Then theanalog image signal is decoded to standard video data ITU-R BT.656. Because thestandard video data decoded by TVP5150has some invalid data, the data extractmodule should be designed. The function of this module is extract the effective image data and separate the odd and even field image data. The valid data is stored via DDRSDRAM, and the DDR controller is designed for dominating the DDR initialization,read and write, refresh and other operations. And moreover, the format of image datacaptured by camera is PAL, but the display system is VGA standard, so the conversionof the corresponding image data which is completed by image de-interlacing andframe rate upgrade module should be needed. If it wants to show gray image only, theY component should be sampled and transmitted to the display system. If it wants toreveal color image, it need to convert YUV format data to RGB format and thenexport the data to display device. The important signals of image display requiredsuch as horizontal and vertical sync signals, field blank signals are received throughthe display control module. The image data can be converted to analog signals viaADV7123.The design, simulation and validation of the whole system are implemented inVHDL on the tool of ISE10.1and validated by the hardware platform which isdesigned based on the chip of XC4VSX25manufactured in Xilinx. This thesis is auseful attempt for the application of the FPGA in the image acquisition system. It alsohas positive meaning in implementing the image acquisition system based on FPGA.