Design And Research Of Class D Audio Power Amplifier Subsystem

With the continuing requirement for energy-efficient and micro-electronic products, low distortion, high efficiency power amplifier design has become a hot topic of the present study. Although the distortion of traditional linear amplifier is small, the efficiency is not high, and traditional linear amplifier requires a large area of the heat sink. Using CMOS technology Class D audio amplifier has the characteristics of high integration, the small size, low power consumption, small heat dissipation, high efficiency, smaller size of the circuit board (PCB) and low cost. In the rapid development of today’s portable electronics market, Class D audio amplifier has been widely used in PDA, mobile phone, MP3player and other products. But most of Class D audio amplifier markets are still monopolized by foreign companies in the domestic portable equipment applications, the study of Class D audio amplifier has great significance in such a situation.This paper mainly carries out a detailed analysis of PWM comparator, dead zone circuit, driving circuit and output stage in each subsystem of Class D audio amplifier. The PWM comparator circuit mainly is made up of differential output by the Rail-to-Rail, secondary amplification, the latche, self-biased amplifiers and output driver and it can effectively reduce the transmission delay and improve the conversion rate. Dead zone circuits are mainly composed by the interlock circuit and effectively control the size of the dead time. It can limit the maximum output power if the dead time is too large and may cause short-circuit between the power supply and the ground if the dead time is too small. It will cause the large current flow through the output stage power transistor which can reduce its service life. Drive circuit is composed mainly by the inverter cascade, the appropriate number of cascade and the magnification can effectively reduce the transmission delay and improve the drive capability. The output stage circuit is mainly composed by full-bridge circuit, this design can effectively reduce the fluctuations of the power bus, get the normal output signal.The circuit uses AMI0.6μm CMOS process, the working voltage is5V, using Spectre tool in the Cadence software on the circuit simulation.The results show that:Input Common Mode Range (ICMR) is0.12~4.8V, the transmission delay is3.6ns, the rising edge of the conversion rate is537V/us, the falling edge of the conversion rate is546V/us in PWM comparator circuit. The rising edge of the dead zone time is1.187ns, the falling edge of the dead zone time is1.191ns, frequency response range is between100Hz-38kHz. When the load resistance is16(?), the output power of the whole circuit is475mW, the efficiency can reach82.663%; When the load resistance is32(?), the output power of the whole circuit is316mW, the efficiency can reach91.221%, the results are consistent with the design requirements.