Research On The Distribution Of The Charges In The Interface Of Si-SiO₂Based On Charge Pumping Technique

The thickness of the gate oxide is continually scaled down with the development of CMOS technologies, which would result in enhancing the gate leakage current drastically. Therefore, the conventional C-V methods could not be suitable for studying hot carrier injection effect in ultra-thin gate oxide MOSFET’s. In this paper, the hot-carrier-effect of0.35μm and0.18μm CMOS device will be investigated, based on charge pumping technique. The scaling down of device dimension effects on HCE will be deeply investigated.The CP method have been further investigated, it is shown that the pulse frequency, reverse voltage, pulse voltage amplitude and duty cycle must be strictly chosen to guarantee the accuracy of measurement. The emission theory of electron and hole was introduced to explain the deviations from the simple CP theory. The high low frequency charge pumping method is proposed for characterizing the interface state in ultra-thin gate oxide CMOS devices. It is successfully demonstrated to separate the leakage current from CP current. It has been proved that the optimal high and low frequency are8MHz and500kHz respectively. These studies can offer experimental guidance and theoretical evidence for measuring the density of interface states and analyzing CP curve in CMOS device.Under the condition of the maximum substrate current, the new degradation phenomenon is shown in0.18μm NMOSFET. Results show that the worst case of hot-carrier induced drain current degradation is characterized at drain voltage higher than0.1V which was well known as the worst condition in long channel device. It can be desired that the degradation of linear drain current as a function of drain voltage, drain voltage increases will lead to decrease of interface states in bandgap and inversion layer charge in channel. Hence, the worst case of characterized Vd is determined by this two competing mechanisms. It is found that the generation of interface trap is responsible for the electrical parameter degradation under Ibmax condition, and linear drain current degradation is the worst. It is also found that the generation of interface states will move toward the saturation after2000s in0.18um NMOSFET. Result shows that electrical parameters degradation is more serious with the scaling down of channel length or width, due to generate more interface states. It is shown that the electrical parameters degradation follows a time power law, and the generation of interface states and electrical parameters is also showing the exponential relationship.Research on hot carrier effect for deep submicron NMOSFET based on MEDICI, it is shown that more hot carrier be injected into gate oxide layer with scaling down of device, induced a lot of traps in the gate oxide layer and at the Si-SiO₂interface. In addition, it is proved that interface traps is one of major inducements of device degradation, the interface traps induced the inversion layer mobility reduction is responsible for the electrical parameter degradation in deep submicron NMOSFET during I_bmax stress.