Research And Design Of Instruction Cache On DSP

Cache compensates for the speed gap between the processor and the DRAM, speeds up memory access, and enhances DSP performance. However Cache is regarded as the main source of processor power because of its large area, fast speed and frequent usage. Therefore how to design a high-performace and low-power Cache is of great significance for the overall performance of the DSP processor and has becomes a spot issue.This paper designed an instruction Cache by adding a line buffer between CPU and Instruction Cache to reduce the on-chip cache memory access activities, consequently it decreased the energy consumption of the Cache memory. What’s more, when Cache miss happens, the refill engine added to the Line Buffer can send instructions from external memory to CPU fetch unit within 6 clocks, which greatly enhanced the performance of instruction Cache. The instruction Cache design included the design of basic parameter, instruction Cache architecture, each functional module and Line Buffer. Among them, in order to reduce the hit time, the workflow of instruction Cache should be defined reasonablely according the the specific characteristics of the DSP.The entire design adopts top-down design process with VHDL for design input, modelsim for function simulation and Design Vision for logic synthesis. The result shows that the design accomplished all expected functions and met the requirements of path delay.In the worst case the longest path delay is 1.66ns. By running three benchmarks, it can be concluded that Line Buffer reduced the frequency of Cache access by 35%, effectively declining the power consumption of the Instruction Cache. The design has been successfully applied to 32bit high-performance DSP, with the overall power consumption below the 0.5mW/MIPS.