Designs Of Low-leakege Power Standard Cells

Leakage power has become the most severe challenge in integrated circuits designs, with thedevelopment of the MOSFFT technology scaling and the integration of continuous improvement.When the process size develops into deep sub-micro, as the power consumption of the leakagebecame more important, the leakage power became increasingly significant from the130nmprocess. At the nanoscale design, the leakage power even accounts for50%the total powerconsumption. The leakage power and dynamic power consumption has become a counterbalanceof the power source. In the low-power design, the low-leakage-power design has become an aspectwhich can not be ignored.The design based on Standard cell is the basis of today’s digital integrated circuit. The qualityand performance of standard cells in IC design is of great importance. Standard cell libraryprovides support for each stage of the flow of digital IC. The quality and performance of standardcells are related to the quality of chip, so it plays an important part in digital chip design. Standardcell is the basis of ASIC design, the low-leakage-power ASIC design and implementation dependson the standard cell of low-leakage-power. Therefore, there is important academic significance andpractical value in the research which is trying to reduce the leakage power consumption of standardcells and to explore the innovative design of standard cell.This paper first introduced the technology and flow of the CMOS low leakage power standardcell library database building and discussed the application of low leakage standard cell in theASIC design. This subject focuses on the research of the low leakage power standard cell packagedesign. Then, we develop the low leakage power performance of the standard unit based on theSMIC130nm CMOS (SMIC13) process, and provides a technical support in low-leakage-powerIC designs.According to the basic principle of standard cell database building, the main research work ofthis paper can be divided into several parts as follows:1. Analysis the SMIC13standard cell library and study the technology of how to reduceleakage power. This paper will introduce how to reduce the power leakage consumption accordingto optimizing the circuit W/L and adopting a new structure of standard cell.2. Finish the layout of the lower leakage power cells, and check all these cells results whetherthey meet SMIC’s lib the design rules. All lower leakage power cells are in strict accordance withthe rule from SMIC’s documents for design process, including standard cell height, width, the display of the PIN and other issues. These rules including metal one layer half spacing rules, whichrequires the metal layer to the boundary a distance is half of the minimum rules. We must followthese rules from SIMC when design these leakage power cells, otherwise, when place and routingusing these lower power leakage cells, it will encounter a lot of errors.3. Complete the P&R library design; finish all of the standard cell’s physical abstractextraction. The abstract step is mainly to extract the shape of metal layer, and the position of thePIN information. The physical library is used for the automatic placement and routing in the digitalIC designs.4. Finish the time and power library extraction of all the cells, complete the cellcharacterization using NCX and HSPICE, and then generate timing and power library which canbe used for logic synthesis.5. Finish an experimental design based on standard cell of my design, then completes theprocess from logic synthesis to placement and routing, and verify the effect of reducing the leakagepower consumption and correctness of the physical rules.