Near-Threshold Sequential Circuit Design

In the last few years, portable electronic devices have been used widely in many areasincluding consumer electronics, medical equipment and industrial instrument, etc. As core ofportable electronic devices, intergret circuit has rapidly developed during the past decades. Speedand area of chips are crucial consideration while the power dissipation has been negelected in theprevious IC design. With the fast development of IC technology, power dissipation has become anincreasingly serious problem which affects IC development.Firstly in nanometer CMOS circiurs, intergration density has been increased effectively onone hand and leakage power dissipation increased expotentially on the other hand with theshrinking channel-length of the transistors. Secondly the first micro processor4004made by Intelcorporation in the1970s which frequency was108KHz. This year Intel showed Core i7microprocessor which frequency was2.9GHz. With high-speed operation, calculation per second ofCPU has imporoved effectively, but it’s also casuing increasing dynamic power dissipation. Howto reduce power disipation has been a hotspot in IC design.Scaling source voltage is a direct and dramatic method to reduce power dissipations due to thequadratic relationship between dynamic power dissipation and supply voltage, but the delay ofcircuit increases inversely with supply voltage. The NCSU PDK45nm CMOS technology isadopted and supply voltages are varied beween nominal supply voltage and threshold voltage inthis paper. Energy Delay Product (EDP) provides a good tradeoff between performance and energyconsumption and as the main quality metric in this paper. This paper is devoted to studying near-threshold sequential circuit and the optimal voltage expolered through the reaserch of flip-flopcharacter in different voltage level. The HSPICE simulation results show that lowering supplyvoltage is advantageous, especially in low voltage region (800mv-900mv) at45nm technology,which yields the best EDP and the optimal supply voltage of the flip-flops varies slightly with logicstyle. Three new structure flip-flops with leakage reduction techniques have proposed and appliedto near-threshold sequential circuits in this paper which provide effective ways for the realizationof near-threshold sequential circuit. The main contents of this paper are shown as follows:The theory of near-threshold circuits is introduced in this paper. This paper investigates sixrepresentative flip-flops in near-threshold regions in terms of explore optimal voltage which yieldslowest EDP (Energy Delay Product).The design of transmission-gate master-slave flip-flop without feedback transmission-gatebased on DTCMOS technique is illustrated and applied to near-threshold mode-10counter in this paper. The HSPICE simulation results show that the proposed flip-flop has better energy, delay andEDP as compared with the conventional one. The proposed flip-flop is an excellent candidate forlow-power design application.The design of ratioed CMOS flip-flop with MTCMOS technique is showed and applied tonear-threshold mode-5counter in this paper. The HSPICE simulation results show that theproposed flip-flop has lower power dissipation when circuit in the standby mode as compared withthe conventional one and can be used for ultra-low power applications which have a relatively longtime in standby mode.The design of ratioed CMOS flip-flop with pulse construction based on channel lengthbiasing technique is showed and applied to near-threshold mode-5counter in this paper. TheHSPICE simulation results show that the proposed flip-flop has less transistors and lower powerdissipation as compared with the conventional one and can be suitable for low-power and high-perfomance application.The standard cell of pulse construction D flip-flop with asynchronous set and reset functionbased on SMIC130nm technology is showed in this paper. The proposed flip-flop has smaller areaand lower power dissipation as compared with the SMIC one. EDA tools simulations show that theproposed cell is an excellent candidate for semi-custom ASIC design which requests low-powerand high performance.