Optimization Of 4T CMOS APS

In recent years, the rapid development of the art of semiconductor industry has narrowed the image quality gap with CCDs to a great degree. In comparison to CCD image sensor, CMOS image sensor has lower power consumption, lower cost and higher integration level. Nowadays CIS has been used in consumer electronics, medical equipment and industrial monitoring etc. The mainstream pixel structure of CMOS image sensor is the 4 transistor (4T) active pixel. The surface dark current can be suppressed by the adoption of the pinned photodiode (PPD) and the reset noise of the pixel can be cancelled by correlated double sampling (CDS). So the research of 4T active pixel is important for the design of high-performance low-noise CMOS image sensorsIn this paper, the mechanism of image lag in 4T pixel has been discussed and the mainstream process of 4T pixel was also presented. Based on the discussion of image lag and process flow, the performance of pixel was improved by applying some adjustments on the process or the PPD shape. All the optimizations are simulated with computer analysis tool Sentaurus-TCAD. For the purpose of improving the collection efficiency, especially for the long wavelength light, two n-type implants were used to form the N layer of the PPD, one with heavy dose and low implant energy the other with light dose and higher implant energy. The combination of these two implants expanded the vertical collection region. The collection efficiency can be improved by about 10% in the long wavelength range. A horizontal gradient doping concentration was also formed in the N layer of PPD by an n-type implant to reduce image lag. A potential barrier likely exists in the pixel that with the size under 2μm was eliminated. The simulation result shows the density of the residual charge is reduced from 2.59×109/cm3 to 2.62×107/cm3. Then the channel of transfer transistor was optimized. An additional P type implant was introduced into the process to adjust the doping concentration under the transfer gate. The potential pocket near the PPD was eliminated,image lag was reduced and the best position of the patent of this implant was found. At last, a new PPD shape was designed for large size pixel. This new PPD shape split the PPD region and the charge could be transferred from around to the center of the pixel. Transfer speed of the pixel will become much faster at the expense of part of the well capacity. This pixel structure fits the command of high speed operation.The design and simulation results in this paper provide lots of useful guides and references on the design of pixel especially for the improvement of beam collection efficiency, the cancellation of image lag and the design of large size pixel.