Sopc-based Speaker Recognition Controller

This passage has built a SOPC embedded system on FPGA which embed an IP soft core in it. A speaker recognition controller was achieved on this embedded system. The platform was DE2-70 development board. It contains a FPGA chip EP2C70 and other rich resources such as audio chip, LCD. memory and so on. There are many methods to build SOPC embed system, and this passage has used NiosⅡprocessor system. The system includes a NiosⅡprocessor and some necessary peripherals such as timers, on-chip RAM and so on. Development tools for NiosⅡprocessor system are QutusⅡ9.0 and SOPC builder. Besides, the development tool for software running in the processor system is NiosⅡ9.0 IDE.Speech Features of the system is linear prediction cepstrum coefficients (LPCC). and matching algorithm is dynamic time warping algorithm (DTW). The recognition depends on both speaker and text, which means system will output an access permission only when the Legitimate user speaks the correct word. System'delay is approximately 8.5ms. It means it can output the recognize result in less than 8.5ms after user finish input his/her voice. To train the templates,10 speakers'voices of the correct word are used, each word pronounces 3 times,. Then, use another voices of the correct word and wrong word, each word for 10 times, to test the templates. Matlab simulation shows that the system's correct identification rate is 99%, and the wrong identification rate is 7.7%.