SOC Testability Research And Implementation

With the continuous improvements in the semiconductor manufacturing technology, the integrate circuit is becoming more and more complex, and hundreds of transistors can be integrated into a silicon die, which is System-on-a-Chip (SOC). The design of SOC mainly adopts the technique of reusable Intellectual-Property (IP) cores, and maps the whole system to a single chip, so it can shorten the time to market, reduce the size of products and improve the performance of the system. It has been widely used in many fields. However, with the increase of the number of IP cores in SOC, test access of IP cores becomes more difficult. It brings more challenges to SOC test. This thesis will discuss the implementation of test structures based on IEEE 1500 standard.This thesis introduces the design for testability of SOC, and deeply studies the IEEE 1500 standard and test scheduling algorithm. Next, a SOC test platform is presented which includes hardware proportion and software proportion in this thesis.The hardware proportion is consisted of computer, interface circuit and FPGA. The testable circuits which meet the IEEE 1500 standard are realized in FPGA, and the design of FPGA also includes a test controller which will analysis test instructions and generate signals needed by the IEEE 1500 standard. The software proportion includes test vectors and test instructions generation module, it can control to achieve fault detection of circuit under test. Because of the test schedule algorithm, the SOC test platform in this thesis can achieve parallel test of multiple IP cores through distribution of the test bus and test order, reducing SOC test time.After the functionally and qualitatively test and analysis, the hardware and software of SOC test platform designed meet the demand. It demonstrates the SOC test, and its excellent performance satisfies the technology requirement completely.