Research On Cache Coherence Protocols For Multi-core Environment

With the requirements of commercial applications and scientific computing on computing capability gradually increase, traditional single-core processor is no longer able to meet various application requirements for computing capability, multi-core processor came into being. Compared with single-core processor, multi-core processor has advantages of easier get high-frequency, low power consumption, low communication latency. But multi-core processor also has limitations and technical challenges. In fact, Cache coherence is a key issue of multi-core processor performance.In recent years, a lot of experts and scholars have in-depth research on Cache coherence issue, focused on snoopy Cache coherence and directory Cache coherence protocols. The results show that reasonable improvement of coherence protocol based on processor architecture can improve system performance effectively.This paper introduces focus and direction of Cache coherence protocol research at home and abroad, and then introduces multi-core processor and storage system, leads out the importance of Cache coherence protocol. Based on the research of Cache working principle and read/write policy, protocol optimization design takes eliminating Cache "pingpang" phenomenon into account. Paper discusses current protocols'limitations:storage overhead, waste of system resources, etc. when protocols applicated in multi-core processor, based on analyze of snoopy Cache coherence and directory Cache coherence protocols. Then, paper presents a new kind of hybrid Cache coherence protocol with D-Cache, which combines write-invalidate and write-update police. MEDSIF revise snoopy protocol's data request process that snoopy protocol only send undifferentiated broadcast to a "Source—D-Cache—Destination" way, while the new way is a point to point comunication process. D-Cache is a small capacity directory, providing addressing and centralized control function for coherence transaction. To avoid the occurrence of Cache ping-pong phenomenon, this protocol design the state set based on the classification of data block copy's number in cores:if write operation acting on two cores'copy between, using write-update; if write operation acting on two cores'copy above, using write-invalidate.Last section, paper discusses the new protocol's correctness, discussed that the new protocol meets the Cache coherence protocol design's requirements:Write Propagation and Write Serialization. At last, multi-core simulator—GEMS was used to test the new protocol's performance. The experiment result figures show that new protocol decreases L1 Cache miss rate and benchmark programs execution time, extent improves system performance.